4 Termination Methods to Teach You to Perfectly Solve Signal Termination Confusion

“In practice, the resistor (R) can be omitted at the output of the buffer because impedance changes dynamically with frequency and impedance matching is difficult to achieve.

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serial termination

In practice, the resistor (R) can be omitted at the output of the buffer because impedance changes dynamically with frequency and impedance matching is difficult to achieve.

Advantage:

Low power solution (no current sink to ground)

It is easy to calculate the value of R R (Z0 C ZOUT).

weakness:

Rise/fall times are affected by RC circuits, increasing jitter

Only valid for low frequency signals

Remark:

CMOS driver

Not suitable for high frequency clock CMOS drivers signal

Ideal for low frequency clock signals and very short traces

pull-down resistor

CMOS

Advantage: very simple (R = Z0)

Weakness: high power consumption

Note: not recommended

LVPECL

Advantage:

Simple 3-resistor solution.

Slightly better in terms of energy savings, saving one resistor versus 4 resistor termination.

Note: Recommended. Termination resistors are placed as close as possible to the PECL receiver.

AC termination

CMOS

Advantage: no DC power consumption.

Note: To avoid higher power dissipation, C should be small, but not so small that it draws current.

LVPECL

Advantage: AC coupling allows bias voltage adjustment. Avoid energy flow between the two ends of the Circuit.

Weaknesses: AC coupling is only recommended for balanced signals (50% duty cycle clock signals).

Note: The ESR value and capacitance of the AC coupling capacitor should be very low.

Resistor Bridge

CMOS

Advantage: Power consumption enables reasonable trade-offs.

Weaknesses: Two devices are used for a single-ended clock.

LVPECL

Weaknesses: 4 external devices for differential output logic.

Note: 3.3V LVPECL drivers are widely used for termination.