“First, let’s take a look at several factors that can affect EMI/EMC: the Circuit structure of the driving power supply; switching frequency, grounding, PCB design, and reset circuit design of the smart LED power supply. Because the original LED power supply is a linear power supply, but the linear power supply will lose a lot of energy in the form of heat during operation. The working...
“Designers of precision signal chains are faced with the challenge of meeting noise performance requirements in medium bandwidth applications, and in the end they often have to make a trade-off between noise performance and accuracy. Shortening the time to market and completing the correct design in the first time further increases the pressure. Duration Σ-Δ (CTSD) ADC has its own architectural advantages, which simplifies the design of the signal chain, thereby reducing the size of the solution and helping customers shorten the time to market of the end product.
Author: ADI Abhilasha Kawle, Senior Analog Design Engineer Wasim Shaikh, Application Engineer
Designers of precision signal chains are faced with the challenge of meeting noise performance requirements in medium bandwidth applications, and in the end they often have to make a trade-off between noise performance and accuracy. Shortening the time to market and completing the correct design in the first time further increases the pressure. Duration Σ-Δ (CTSD) ADC has its own architectural advantages, which simplifies the design of the signal chain, thereby reducing the size of the solution and helping customers shorten the time to market of the end product. In order to illustrate the advantages of CTSD ADC architecture and how it is suitable for various precision medium bandwidth applications, we will deeply analyze the signal chain design, let designers understand the key advantages of CTSD technology, and explore the easy-to-design features of the AD4134 precision ADC.
In many digital processing applications and algorithms, in the past 20 years, all converter technologies are increasingly required to have higher resolution and accuracy. By using an external digital controller, software techniques such as averaging and optimized filtering schemes can be used to extract and provide more accurate results, thereby improving the resolution/accuracy of the ADC. In order to reduce the large amount of post-processing work for digital microcontrollers or DSPs, designers can use high-performance precision ADCs. This will reduce the digital optimization time, and you can also consider using a lower-cost microcontroller or DSP. The applications and markets of precision ADCs are extensive:
► Industrial instrumentation: vibration analysis, temperature/pressure/stress/flow measurement, dynamic signal analysis, acoustic analysis
Figure 1. Example of a precision ADC signal chain
► Medical instruments: electrophysiology, blood analysis, electrocardiogram (EKG/ECG)
► Defense applications: sonar, telemetry
► Test and measurement: audio test, hardware loop, power quality analysis
The analog input signal processed by the ADC can be a sensor signal with voltage and current output, or a feedback control loop signal with a bandwidth ranging from DC to several hundred kHz. The ADC digital output format and rate depend on the application and post-processing required by the following digital controller. Generally speaking, the signal chain designer follows the Nyquist sampling criterion and sets the ADC output data rate (ODR) of the digital controller to at least twice the input frequency. Most ADCs allow flexible adjustment of the output data rate based on the relevant signal frequency band.
For currently available ADCs, several signal conditioning stages are involved before the ADC can interact with the input signal. Signal conditioning circuits with strict requirements need to be designed and customized around specific and individual ADC technologies to ensure that the performance of the ADC data sheet can be achieved. After choosing ADC, the work of the signal chain designer is not over. It usually takes a lot of time and effort to design peripherals and make adjustments. ADI’s design simulation tools and Model libraries can provide designers with technical support to help them cope with design challenges.
New method: Simplify the design journey with the CTSD architecture
The CTSD architecture is mainly used for audio and high-speed ADCs, and is now tailored for precision applications to achieve high accuracy while taking advantage of its unique signal chain simplification characteristics. Using this architecture can reduce the workload of designing peripherals. Figure 2 shows how to use this new solution to achieve high channel density, simplifying and reducing the current ADC signal chain by 56%. The figure is just a small part of it.
In order to illustrate how CTSD ADC technology simplifies signal chain design, this article focuses on some of the key challenges involved in the existing signal chain for general applications and demonstrates how CTSD ADC can alleviate these challenges.
Therefore, we first introduce several design steps involved in the existing signal chain. The first task is to select the correct ADC for the target application.
Step 1: Choose ADC
In addition to the resolution and accuracy of the final digital output required by the application, signal bandwidth, ODR, signal type, and range to be processed are also important considerations when selecting the appropriate ADC from the wide range of available. Generally speaking, in most applications, digital controllers require the use of algorithms to process the amplitude, phase, or frequency of the input signal.
In order to accurately measure any of the preceding factors, it is necessary to minimize the error added during the digitization process. The main errors and their corresponding measurement terms are detailed in Table 1, and further detailed instructions are provided in the Basic Guide to Data Conversion.
Table 1. ADC Error and Performance Index
Related measurements in the data sheet
Thermal and quantization noise
Signal-to-noise ratio (SNR), dynamic range (DR)
Total harmonic distortion (THD), intermodulation distortion (IMD)
Crosstalk, alias suppression, power supply voltage rejection ratio (PSRR), common mode rejection ratio (CMRR)
Amplitude and phase error
Gain error, amplitude and phase drop at target frequency
Delay from ADC input to final digital output
Delay, settling time
The performance indicators in Table 1 are related to signal amplitude and frequency, and are usually referred to as AC performance parameters.
For DC or near-DC applications, such as power metering for processing 50 Hz to 60 Hz input signals, ADC errors such as offset, gain, INL, and flicker noise must be considered. These DC performance parameters also need to have a certain temperature stability for the intended use of the application.
ADI provides a variety of industry-leading high-performance ADCs to meet the system requirements of multiple applications, such as applications based on accuracy, speed, or limited power budgets. Only comparing the two sets of ADC specifications is not enough to select the ADC correctly. The overall system performance and design challenges must also be considered, which is the key to choosing ADC technology or architecture. Two major categories of ADC architectures are traditionally preferred. Commonly used is the successive approximation register (SAR) ADC, which follows the simple Nyquist criterion. It points out that if it is sampled at twice its frequency, the signal can be reconstructed. The advantages of SAR ADC are excellent DC performance, small size, low latency, and power consumption adjustment through ODR.
The second technical option is a discrete-time sigma-delta (DTSD) ADC, which works on the principle that the larger the number of samples, the less information is lost. Therefore, the sampling frequency is much higher than the specified Nyquist frequency. This scheme is called oversampling. Another advantage of this architecture is that the error added due to sampling can be minimized within the target frequency band. Therefore, DTSD ADC has both excellent DC and AC performance, but the delay is relatively high.
Figure 2. Small size solution with ADI’s easy-to-use new CTSD ADC
Figure 3 shows the typical analog input bandwidths of SAR and DTSD ADCs, as well as some common product choices with different speeds and resolutions. You can also use the precise quick search function to help you choose an ADC.
In addition, a new type of precision ADC is now available. These ADCs are based on DTSD ADCs, which are comparable in performance to DTSD ADCs, but have unique advantages in simplifying the entire signal chain design process. This new ADC series can solve the more prominent challenges in the subsequent design steps of the existing signal chain.
Step 2: Input and ADC interface
The sensor whose output is processed by the ADC may have very high sensitivity. The designer must clearly know the ADC input structure that the sensor will interface with to ensure that the ADC error does not affect or distort the actual sensor signal.
In traditional SAR and DTSD ADCs, the input structure is called a switched capacitor sample-and-hold Circuit, as shown in Figure 4. At the edge of each sampling clock, when the sampling switch changes its ON/OFF state, it needs to support the limited current demand in order to charge and discharge the holding capacitor to a new sampling input value. This current needs to be provided by an input source. In the example we are discussing, this input source is a sensor. In addition, the switch itself has some on-chip parasitic capacitance, which will inject some charge into the power supply, which is called charge injection kickback. The resulting error source also needs to be absorbed by the sensor, so as not to adversely affect the sensor signal.
The inability of most sensors to provide this current magnitude indicates that they cannot directly drive the switching circuit. In another case, even if the sensor can support these current requirements, the finite impedance of the sensor will add error at the ADC input. The charge injection current is a function of the input, and this current will cause an input-related voltage drop on the sensor impedance. As shown in Figure 4a, the ADC input is wrong. Placing a drive amplifier between the sensor and ADC can solve these problems, as shown in Figure 4b.
Now we need to set the standard for this amplifier. First, the amplifier should support the charging current and be able to absorb the charge injection kickback. Second, the output of the amplifier needs to be completely stable at the end of the sampling edge, so that the ADC input sampling does not increase the error. This means that the amplifier should be able to provide instantaneous current steps, mapped to have a high slew rate, and provide a fast settling response to these transient events, mapped to have a high bandwidth. As the sampling frequency and resolution of ADCs increase, it becomes critical to meet these requirements.
A major challenge faced by designers, especially those dealing with mid-bandwidth applications, is to determine the appropriate amplifier for the ADC. As mentioned earlier, ADI provides a set of simulation models and precision ADC driver tools to simplify this step, but for designers, this is an additional design step to achieve ADC data sheet performance. Some new-age SAR and DTSD ADCs use novel sampling techniques to completely reduce transient current requirements, or use integrated amplifiers to meet this challenge. But both of these solutions limit the range of the signal bandwidth or impair the performance of the ADC.
Advantages of CTSD ADC: CTSD ADC solves this problem by providing new options for easy-to-drive resistive inputs instead of switched capacitor inputs. This shows that there are no hard requirements for high bandwidth, high slew rate amplifiers. If the sensor can directly drive this resistive load, it can be directly interfaced with the CTSD ADC; otherwise, any low-bandwidth, low-noise amplifier can be connected between the sensor and the CTSD ADC.
Figure 3. Precision ADC architecture positioning
Figure 4. (a) Switched capacitor charge injection backlash to the sensor, (b) using input buffer to isolate the kickback effect
The third step: reference voltage source and ADC interface
The challenges involved in interfacing with a reference voltage source are similar to those of an input interface. The input of the reference voltage source of the traditional ADC is also a switched capacitor. At each sampling clock edge, the reference voltage source needs to charge the internal capacitance, so a large switching current with good settling time is required.
The available reference voltage source ICs do not support large switching current requirements and have limited bandwidth. The second interface challenge is that the noise from these references is greater than the noise of the ADC. In order to filter out this noise, a first-order RC circuit is used. On the one hand, we limit the bandwidth of the reference voltage source to reduce noise. On the other hand, we need a fast settling time. These are two opposing requirements that need to be met at the same time. Therefore, use a low-noise buffer to drive the ADC reference pin, as shown in Figure 5b. The slew rate and bandwidth of this buffer are determined based on the sampling frequency and resolution of the ADC.
Similarly, like our precision input driver tools, ADI also provides tools for ADC simulation and selection of the correct reference voltage source buffer. Like the input, some new-age SAR and DTSD ADCs also offer integrated reference buffer options, but they have performance and bandwidth limitations.
Advantages of CTSD ADC: Using CTSD ADC can completely skip this design step, because it provides a new and convenient option for driving resistive loads without the need for such high bandwidth, high slew rate buffers. The reference voltage source IC with low-pass filter can directly interface with the reference pin.
Step 4: Make the signal chain free from interference
Sampling and digitizing a continuous signal will cause loss of information, which is called quantization noise. The sampling frequency and number of bits determine the performance limitations of the ADC architecture. After solving the performance and interface challenges of the reference voltage source and input, the next problem is to solve the problem of high frequency (HF) interference source/noise folding to the target low frequency bandwidth. This is called aliasing or foldback. These high-frequency or out-of-band interference sources that enter the target bandwidth result in a reduction in signal-to-noise ratio (SNR). According to the sampling criterion, any signal tones around the sampling frequency will be folded back in the band, as shown in Figure 6, generating unnecessary information or errors in the target frequency band. For more detailed information about aliasing, see tutorial MT-002: What Does the Nyquist Criterion Mean for Data Sampling System Design.
Figure 5. (a) Switched capacitor charge injection kickback to the reference voltage source IC (b) Using the reference voltage source buffer to isolate the kickback effect
Figure 6. Out-of-band interference source aliasing/folding back into the target frequency band due to sampling
Figure 7. Using anti-aliasing filters to mitigate aliasing effects on in-band performance
One solution to alleviate the foldback effect is to use a low-pass filter called an anti-aliasing filter (AAF) to attenuate the amplitude of unnecessary interference sources, so that when the attenuated interference source folds back into the band, it can maintain The required signal-to-noise ratio. The low-pass filter is usually integrated with a driver amplifier, as shown in Figure 7.
When designing this amplifier, the biggest challenge is to find a balance between fast settling and low-pass filtering requirements. Another challenge is that the solution needs to be fine-tuned for each application requirement, which limits the use of a single platform design for each application. ADI has many anti-aliasing filter tool designs that can help designers overcome this challenge.
The advantage of CTSD ADC: This kind of immunity can be solved by the aliasing suppression characteristic of CTSD ADC itself, which is a unique characteristic of CTSD ADC. ADCs using this technology do not require AAF. Therefore, we are expected to directly connect the CTSD ADC to the sensor, which is one step closer to this goal.
Step 5: Select ADC clock frequency and output data rate
Next, let’s discuss the clock requirements of the two traditional ADC types. DTSD is an over-sampled ADC, which refers to an ADC that samples the ADC at a sampling rate higher than the Nyquist sampling rate. However, if the ADC oversampled data is directly provided to an external digital controller, a large amount of redundant information will overload it. In an oversampling system, the core ADC output uses an on-chip digital filter for decimation, so that the final ADC digital output data rate is lower, usually twice the signal frequency.
For DTSD ADC, designers need to plan to provide a high-frequency sampling clock for the core ADC and set the required output data rate. The ADC will provide the final digital output on this required ODR and ODR clock. The digital controller uses this ODR clock to input data.
Next, we address the clock requirements of the SAR ADC, usually following the Nyquist criterion. Here, the sampling clock of the ADC is provided by the digital controller, and the clock also serves as the ODR. However, due to the need to effectively control the sample and hold timing to obtain the excellent performance of the ADC, the timing flexibility of this clock is low, which also indicates that the digital output timing needs to be as consistent as possible with these requirements.
Figure 8. Clock requirements for (a) DTSD ADC and (b) SAR ADC
After understanding the clock requirements of these two architectures, you can see that the ODR is coupled to the sampling clock of the ADC. This is a limiting factor in many systems where the ODR can dynamically drift or change or need to be tuned to the frequency of the analog input signal.
Advantages of CTSD ADC: CTSD ADC can be coupled with the new asynchronous sampling rate converter (ASRC), which can resample the core ADC with any required ODR. ASRC also enables designers to accurately set ODR to any frequency and breaks through the old limitation of restricting ODR to multiples of the sampling frequency. The frequency and timing requirements of the ODR are now completely within the functional scope of the digital interface and have nothing to do with the ADC sampling frequency. This feature simplifies digital isolation design for signal chain designers.
Step 6: Interface with external digital controller
Traditionally, there are two types of data interface modes for ADC and digital controller communication. One type uses the ADC as a host, provides a digital/ODR clock, and determines the clock edge of the digital controller to input ADC data. The other type is the managed mode (receiver mode), where the digital controller is the host, provides the ODR clock, and determines the clock edge of the input ADC data.
Starting from step 5, if the designer chooses the DTSD ADC, the ADC will provide the ODR clock and therefore act as the host of the digital controller that follows. If the SAR ADC is selected, the digital controller needs to provide the ODR clock, which means that the SAR ADC will always be configured as a managed peripheral. Therefore, there are obvious limitations: Once the ADC architecture is selected, the digital interface is limited to host mode or managed mode. Currently, no matter what the ADC architecture is, there is no way to flexibly choose an interface.
Advantages of CTSD ADC: The new ASRC combined with CTSD ADC enables designers to independently configure the ADC data interface mode. This opens up brand-new opportunities for some applications. In these applications, regardless of ADC architecture, high-performance ADCs can be configured in any mode suitable for digital controller applications.
Connect the devices
Figure 9 shows the building blocks of a traditional signal chain. The analog front end (AFE) includes an ADC input driver, an alias suppression filter, and a reference buffer that can be greatly simplified by the CTSD ADC. Figure 10a shows an example signal chain using a DTSD ADC, which requires a lot of design work to fine-tune and determine the ADC’s data sheet performance. In order to simplify the customer process, ADI provides reference designs that can be reused or re-adjusted for various applications of these ADCs.
Figure 10b shows the signal chain with a CTSD ADC and its simplified analog input front end (AFE), because the ADC core does not have a switched capacitor sampler at the input and reference voltage source ends. The switch sampler is moved to the latter stage of the ADC core, so that the signal input and the reference voltage source input are purely resistive. This results in an ADC with almost no sample aliasing, making it a class of its own. In addition, the signal transfer function of this type of ADC simulates the response of an anti-aliasing filter, which means that it can attenuate noise sources by itself. Using CTSD technology, the ADC can be simplified into a simple plug-and-play component.
In short, CTSD ADC simplifies the design of the signal chain, and at the same time realizes a system solution with the same level of performance as the traditional ADC signal chain, and has the following advantages:
► Provides an alias-free, low-delay signal chain with excellent phase matching between channels
► Simplifies the analog front end, no need to select and fine-tune the extra steps of high-bandwidth input and reference voltage source drive buffer, which can achieve higher channel density
► Break the barrier of ODR as a function of sampling clock
► Independent control interface with external digital controller
► Improved the reliability rating of the signal chain, which is the benefit of the reduction of peripheral components
► Reduced size and BOM by 56%, shortening the time to market for customers
The next article in this series will explore how CTSD ADC and ASRC can help simplify signal chain design. The next few articles in this series will introduce the concepts of CTSD ADC and ASRC in more detail, highlight the advantages of the signal chain, and finally introduce how to use the features of the new product AD4134. Stay tuned to learn more about the breakthrough CTSD and ASRC technologies that help simplify design!
Figure 9. Signal chain building blocks using traditional precision ADC and CTSD ADC respectively
Figure 10. Example signal chain using (a) DTSD technology and (b) CTSD technology