On January 26, Wu Jihan, co-founder of Bitmain, officially announced his resignation as CEO and chairman of Bitmain through an encrypted letter. The rhythm BlockBeats unraveled the content of the letter through the password posted by Wu Jihan on Twitter. Jihan Wu explained the final solution to the struggle with Ketuan Zhan in English. At the same time, he also firmly believed that Bitmain would s...
Routers, switches and line cards require higher bandwidth, port density, and up to 800GbE connectivity to handle escalating data centre traffic driven by 5G, cloud services and AI and ML applications. Delivering the higher bandwidth, these designs must overcome the signal integrity challenges associated with the industry’s transition to the 112G PAM4 SerDes connectivity required to support the latest pluggable optics, system backplanes and packet processors. These challenges can now be overcome with what is claimed to be the industry’s most compact, 1.6T, low-power PHY solution from Microchip Technology with its PM6200 META-DX2L that reduces power per port by 35% compared to its 56G PAM4 predecessor, META-DX1, the industry’s first terabit-scale PHY solution.
“The industry is transitioning to a 112G PAM4 ecosystem for high-density switching, packet processing, and optics,” said Bob Wheeler, principal analyst for networking at The Linley Group. “Microchip’s META-DX2L is optimised to address these demands by bridging line cards to switch fabrics and multi-rate optics for 100 GbE, 400 GbE and 800 GbE connectivity”.
With its high-density 1.6T bandwidth, space-saving footprint, 112G PAM4 SerDes technology, and support for Ethernet rates from 1GbE to 800GbE, this Ethernet PHY is an industrial-temperature-grade device that provides the connectivity versatility to maximise design reuse over applications varying from a retimer, gearbox or reverse gearbox to a hitless 2:1 mux. Highly configurable crosspoint and gearbox features make extensive use of a switch device’s I/O bandwidth to facilitate the flexible connections required for multi-rate cards that support a wide range of pluggable optics. The PHY’s low-power PAM4 SerDes allows it to support the next-generation infrastructure interface rate for cloud data centres, AI/ML compute clusters, 5G, and telecom service provider infrastructure, whether across long-reach DAC cables, backplanes, or connections to pluggable optics.
“For the 56G generation, we introduced the industry’s first terabit PHY, META-DX1, and now we have followed with an equally transformative 112G solution that delivers the capabilities system developers need to solve today’s new challenges posed by cloud data centres, 5G networking, and AI/ML compute scale-out,” said Babak Samimi, vice president for Microchip’s communications business unit. “By delivering up to 1.6T of bandwidth within a low-power architecture and in the smallest footprint, the META-DX2L PHY doubles the bandwidth of previous solutions on the market while establishing a new level of power efficiency.”