“Short-Circuit the output of the module under various input and output states, the module should be able to achieve protection or retraction, and short-circuit repeatedly for many times. After the fault is eliminated, the module should automatically resume normal operation. “ 1 Repeated short circuit test◆ Test description Short-circ...
Mountain View, California, December 3, 2021 — Synopsys, Inc. (NASDAQ: SNPS) announced that since the official release of the Fusion Compiler™ RTL-to-GDSII solution in 2019, Customers who have adopted this solution have achieved more than 500 tape-outs. As a result, Synopsys has further expanded its leading advantage in the field of digital design. Many leading semiconductor companies from high-growth vertical fields such as high-performance computing (HPC), artificial intelligence (AI) and 5G mobile use Fusion Compiler to successfully tape out films at the 40nm to 3nm process node.
How to achieve strict performance, power consumption, and area (PPA) goals in a tight time and under advanced process nodes is a severe challenge faced by many developers at this stage. Synopsys Fusion Compiler, with its unified architecture and optimization engine, can assist developers in achieving sign-off accurate PPA indicators, and greatly reduce design iterations and later accidents. According to estimates, compared with other solutions in the industry, the Fusion Compiler solution can help customers achieve a 20% increase in performance, a 15% reduction in power consumption, and a 5% reduction in area on average.
Ilyong Kim, vice president of the LSI business design technology team of Samsung Electronics, said: “We have achieved excellent quality of results through the close production deployment of Synopsys Fusion Compiler solutions, including significantly improved utilization and faster time to market, thereby improving the industry. Leadership. Its unique single-data Model and unified engine, as well as built-in sign-off level timing analysis, parasitic parameter extraction and power analysis, help us reduce design iterations and stand out among many industry solutions. We have successfully designed many times The advantages of Fusion Compiler are felt in the tape-out. We are currently expanding deployment and plan to adopt Synopsys’ latest machine learning technology to further deepen our customer-centric differentiation advantage.”
Kazunari Horikawa, Senior Manager of Design Technology Innovation Department of Kioxia, said: “Kazunari Horikawa is a leading memory supplier in the semiconductor industry and is in a leading position in the production of high-performance memory controllers. Through cooperation with Synopsys, we have achieved a complete The Fusion Compiler design process has significantly improved process efficiency. In addition, with the help of Synopsys TestMax product test fusion technology, we can shift the design method to the left and reduce power consumption by 40% and area reduction by 10% in the latest tape-out , Which further enhances our leadership in the industry. We look forward to working with Synopsys to use Fusion Compile solutions to further increase productivity.”
A production-proven and scalable data model to assist customers in obtaining predictable quality of results
Fusion Compiler is the industry’s only RTL-to-GDSII product that supports a single data model and golden sign-off standard. It uses a unified data model with high scalability and includes analysis techniques in the industry’s golden sign-off tools. These functions are all encapsulated in an integrated environment to deliver a unique customized process to achieve predictable quality of results (QoR) and sign-off relevance. In addition, “Ubiquitous Machine Learning” technology further enhances the unique architecture of the product, bringing productivity and QoR to a higher level.
“Our customers continue to be under pressure to provide solutions to new markets within a tight time frame. Through Fusion Compiler, they can accelerate their products to the market while providing differentiated PPA,” Synopsys Digital Realization Division Marketing Sanjay Bali, vice president of strategy, said: “Our customers have achieved more than 500 tapeouts with Fusion Compiler, which once again proves that the market needs a vertically integrated RTL-to-GDSII solution to achieve the ideal PPA goal.”
Fusion Compiler is the core of Synopsys Fusion Design Platform™. As the industry’s first AI-enhanced cloud design solution, Fusion Design Platform redefines the boundaries of traditional EDA tools such as logic synthesis, placement and routing, and sign-off verification. It uses machine learning to accelerate computationally intensive analysis, predicts results to improve decision-making, and uses learning from past experience to achieve better results.
At the recent Synopsys Digital Design Technology Symposium (Synopsys Digital Design Technology Symposium), AMD, Arm, MediaTek and other customers introduced in detail their design experience using Fusion Compiler and Fusion Design Platform.