With the popularization of 5G communication and new energy vehicles, there is an increasing demand for high-efficiency power supplies. The key factor to improve the power conversion efficiency lies in the power part of the switching power supply.
Many high-performance, high-frequency PWM control chips, whether digital or analog, have no or limited ability to directly drive power MOSFETs. Because the power MOSFET has high requirements on the gate drive current, the driver chip is equivalent to the bridge between the PWM switch control chip and the power MOSFET, which is used to amplify the switching signal current and voltage, and has a certain fault isolation capability. Once a certain switching power supply scheme is determined, the next step is to select a suitable driver IC, and to select a driver chip, the hardware engineer needs to have a certain understanding of the Circuit characteristics.
Taking a typical AC/DC switching power supply system as an example, the PFC part adopts a bridgeless boost topology, and an NSD1025 can be used to drive two switching MOSFETs at the same time. The primary side of the LLC can use a half-bridge isolation driver chip NSi6602 to drive the upper and lower bridges at the same time. The arm MOSFET, the secondary side uses an NSD1025 to drive the full-wave synchronous rectification MOSFET. Selecting high-speed and high-reliability driver ICs can help power systems improve efficiency and power density.
Because switching power supplies often require hard switching to drive high-power loads, under hard switching and layout constraints, power MOSFETs tend to form large ground bounce voltages and oscillating peak voltages on the input and output terminals of the driver chip. The ground bounce voltage will cause an equivalent negative voltage at the driver input, and most gate drivers can withstand a certain negative voltage pulse due to the internal equivalent body diode. However, it is also necessary to take precautions to prevent excessive overshoot and undervoltage spikes at the input of the driver, which may damage the driver chip or cause malfunction.
Reasons for the formation of negative pressure spikes at the drive input
Still taking the PFC topology as an example, the low-side driver is used between the control chip and the power MOSFET to help reduce switching losses and provide enough drive current for the MOSFET to cross the Miller plateau region for fast turn-on. When switching the MOSFET, a high di/dt pulse is generated. This rapid change, combined with the parasitic inductance, produces a negative voltage peak, which can be estimated using the formula Vn = Lss* di/dt. Lss stands for parasitic inductance. The value of the parasitic inductance is approximately equal to the sum of the inductances in the internal bonding wire of the power MOSFET and the ground loop of the PCB return line.
As can be seen from the above equation, the negative voltage is proportional to both the parasitic inductance and the rate of change of the current. In a typical low-side gate drive circuit, although the controller and power MOSFET use the same DC ground plane as a reference, in some cases there will always be parasitic inductance due to the distance between the driver and controller. When the high di/dt current flows through the MOSFET and its board-level loop, the presence of parasitic inductance will cause the ground potential of the driver to rise instantaneously relative to the ground potential of the controller, which is equivalent to an instantaneous negative voltage between the input of the driver and the ground. . In extreme cases, the input ESD device inside the driver may be damaged, and the driver may fail.
Another common scenario where negative input voltage occurs is related to current sampling of MOSFETs. In order to achieve more precise control, sometimes a sampling resistor is connected between the power MOSFET and the ground, and this sampling resistor is used to detect the current flowing through the MOSFET, so that the controller can respond quickly. In order to make the driving loop of the MOSFET small enough, the GND pin of the driver and the source of the MOSFET are connected together, and the GND of the control chip and the real ground plane are together, so that the GND of the driver and the GND of the control chip are connected together. There will be a bias voltage, so when the control chip outputs a low level, there is a negative bias voltage relative to the input terminal of the driver.
How to deal with negative pressure at the input
There are generally three solutions to the instantaneous negative voltage of the input caused by parasitic inductance. First, the influence can be reduced by reducing the switching speed. Reducing the switching speed can reduce the current change rate di/dt, and the instantaneous negative voltage amplitude will also decrease. However, this treatment has side effects, reducing the switching speed will increase the conversion time, so it will increase the switching loss, and in some applications, if the response time is required, the method of reducing the switching speed may not be suitable.
The second method is to optimize the PCB layout as much as possible, reduce parasitic parameters, and thus reduce the negative pressure peak. This is a common method in system design, but it requires hardware engineers to have very rich design experience, and some design conditions are limited. , it may not be possible to optimize the PCB layout
The third method is to choose a device with strong anti-interference ability, such as the new non-phase dual-channel high-speed gate driver NSD1025 from Nanochip Microelectronics. By optimizing the ESD structure at the input end, NSD1025 can withstand a maximum input voltage of -10V. Compared with other competing products, NSD1025 can better deal with transient negative pulses in common application scenarios and has better reliability.
Experienced engineers typically consider all three immunity options simultaneously, and then arrive at the optimal choice based on application constraints. However, choosing a device with strong anti-interference ability will undoubtedly bring more fault tolerance and choice for the design of the entire system, so it becomes the first step for engineers in system design.
In addition to the ability to withstand negative pressure, NSD1025 also provides an under-voltage lockout function to keep the output low until the power supply voltage enters the working range, and the hysteresis function between the high and low thresholds also provides better anti-interference ability. Ideal for applications such as power systems, motor controllers, linear drivers, and wide-bandgap power device drivers such as GaN.
After NSD1025, Nanochip will also launch 600V high and low side drivers, as well as 600V high and low side driver chips specially designed for GaN. It can bring better solutions for engineers in the anti-interference design of industrial power supply, motor drive and other applications.